The present invention relates to a semiconductor storage device, more specifically to a semiconductor storage device structure which enables highly-integrated DRAMs (Dynamic Random Access Memories) to be fabricated within tiny cell areas and by a small number of fabrication steps, and a method for fabricating the semiconductor storage device structure.
A DRAM is a semiconductor storage device which can be formed of one transistor and one capacitor. Various structures of the DRAM and various methods for fabricating the DRAM have been conventionally studied to fabricate semiconductor storage devices of higher density and higher integration.
FIG. 59 shows a sectional view of the semiconductor storage device described in Japanese Patent Laid-Open Publication No. 176148/1986.
Source diffused layers 24 and drain diffused layers 26 are formed on a semiconductor substrate 10 independent of each other. Gate electrodes 20 are formed, through gate oxide films 16, on parts of the semiconductor substrate 10 between the respective source diffused layers 24 and the respective drain diffused layers 26. Memory cell transistors thus comprising the gate electrodes 20, the source diffused layers 24 and the drain diffused layers 26 are constituted.
On the semiconductor substrate 10 with the memory cell transistors formed thereon there are formed inter-layer insulation film 36 having through-holes 38 which are opened on the drain diffused layers 26 and through-holes 40 which are opened on the source diffused layers 24.
Cylindrical capacitor storage electrodes 46 of polycrystalline silicon are formed on the inside walls of the through-holes 40 and have their bottoms connected to the source diffused layers 24.
Capacitor dielectric films 48 are formed on the inside walls and upper surfaces of the capacitor storage electrodes 46, and parts of the upper surfaces of the source diffused layers 24 exposed inside the through-holes 40.
Capacitor opposed electrodes 54 are formed in the through-holes 40 with the capacitor storage electrodes 46 and the capacitor dielectric films 48 formed thereon, and on the inter-layer insulation film 36. Capacitors thus comprising the capacitor storage electrodes 46, the capacitor dielectric films 48 and the capacitor opposed electrodes 54 are formed.
Polycrystalline silicon is buried in the through-holes 38 and is connected to bit lines 62 through an inter-layer insulation film 53 formed on the capacitor opposed electrodes 54.
Furthermore, a metal wiring layer (not shown) is formed on the top of the bit lines through an inter-layer insulation film (not shown), and a DRAM comprising one-transistor and one-capacitor memory cells is formed.
FIG. 60 shows a sectional view of another semiconductor storage device.
Source diffused layers 24 and drain diffused layers 26 are formed on a semiconductor substrate 10 independent of each other. Gate electrodes 20 are formed, through gate oxide films 16, on parts of the semiconductor substrate 10 between the source diffused layers 24 and the drain diffused layers 26. Memory cell transistors thus comprising the gate electrodes 20, the source diffused layers 24 and the drain diffused layers 26 are constituted.
On the semiconductor substrate 10 with the memory cell transistors formed thereon, there are formed inter-layer insulation film 102 having through-holes 98 which are opened on the drain diffused layers 26 and through-holes 100 which are opened on the source diffused layers 24. Insulation films 42 are formed on the gate electrodes 20, covering the same. Exposed parts of the insulation films 42 in the through-holes 98, 100 are defined by the insulation films 42.
An inter-layer insulation film 36 is formed on the inter-layer insulation film 102. Capacitor storage electrodes 46 of polycrystalline silicon are formed on the inside walls and the bottoms of through-holes 40 formed in the inter-layer insulation film 36. The capacitor storage electrodes 46 are connected to the source diffused layers 24 through polycrystalline silicon films 104 buried in the through-holes 100.
Capacitor dielectric films 48 are formed on the inside surfaces and the upper surfaces of the capacitor storage electrodes 46. Capacitor opposed electrodes 54 are formed in the through-holes 40 with the capacitor storage electrodes 46 and the capacitor dielectric films 48 formed thereon, and on the inter-layer insulation film 36. Capacitors thus comprising the capacitor storage electrodes 46, the capacitor dielectric films 48 and the capacitor opposed electrodes 54 are formed.
Polycrystalline silicon films 106 are buried in the through-holes 98 and are connected to bit lines 62 formed on the capacitor opposed electrodes 54 through the inter-layer insulation film 53.
A metal wiring layer (not shown) is formed on the bit lines through an inter-layer insulation film (not shown), and a DRAM comprising one-transistor and one-capacitor memory cells is formed.
To form DRAM cells, usually 9 lithography steps are necessary for the LOCOS isolation, the formation of the gate electrodes (word lines), the bit line contact holes, the bit lines, the through-holes for the capacitor storage electrodes, the capacitor storage electrodes, the capacitor opposed electrodes, the through-holes for the metal wiring, and the metal wiring.
In lithography steps, an alignment allowance for the gate electrodes and the bit line contact holes, an alignment allowance for the gate electrodes and the through-holes, and an alignment allowance for the though-holes and the bit lines are necessary, which makes the memory cell area accordingly larger.
To improve this disadvantage, the semiconductor storage device described in Japanese Patent Laid-Open Publication No. 176148/1986 uses the above-described structure, so that the capacitor storage electrodes are formed by self-alignment with the through-holes, whereby the lithography steps are decreased by one step.
In the semiconductor storage device of FIG. 60, the capacitor storage electrodes are formed by self-alignment, and in addition thereto the through-holes 98, 100 are formed by self-alignment with the gate electrodes, whereby no alignment allowances for the gate electrodes and the through-holes for the bit line contact and for the gate electrodes and the through-holes for the capacitor storage electrodes are necessary. This can accordingly decrease the memory cell area.
The fabrication of a semiconductor storage device which can be highly integrated by a smaller number of lithography steps and with smaller alignment allowances has been thus proposed.
In the semiconductor storage device described in the specification of Japanese Patent Laid-Open Publication No. 176148/1986, a polycrystalline silicon film is deposited to form the capacitor storage electrodes 46, concurrently being buried in the through-holes 38, whereby the above-described structure is formed. The reason for completely filling the through-holes is as follows.
As disclosed in the specification, the bit lines 62 are made of aluminium (Al) and they thus are the uppermost wiring layer. In addition, to contact the Al to the source-drains or the gate electrodes for peripheral circuits, it is necessary that the insulation film is etched by a larger thickness than a thickness of the bit line contact. The inter-layer insulation film 36 of the bit line contact, however, has no trace of etching, and it is presumed that the peripheral circuit through-holes as well as the through-holes 38 are completely filled with polycrystalline silicon.
The peripheral circuit through-holes are thus completely filled because a contact resistance of a peripheral circuit greatly affects efficiency of operation speed of the circuit, and preferably the through-holes are completely filled to reduce the contact resistance as much as possible. Accordingly, it is necessary to completely fill the bit line contact through-holes concurrently with filling the peripheral circuit through-holes.
In the semiconductor storage device disclosed in Japanese Patent Laid-Open Publication No. 176148/1986, the polycrystalline silicon film buried in the peripheral circuit through-holes must be thicker than a through-hole diameter. This is because since the capacitor storage electrodes 46 are concurrently formed of the polycrystalline silicon, the polycrystalline silicon film of an excessive thickness will decrease an inside wall area of the through-holes 40, with a result of a decreased cell capacitance.
When the through-holes 38, 40 are formed, an alignment allowance for the gate electrodes 20 must be taken into consideration. This increases a cell area and decreases a capacitor forming part.
In the semiconductor storage device of FIG. 60, as described above, the self-alignment contact is formed, and in forming the through-holes 98, 100 it is not necessary to consider an alignment allowance for aligning the though-holes 98, 100 with the gate electrode 20. The though-holes 40 and the bit line contact hole 58 are formed separately from each other, and the bit line contact holes 58 are not filled with polycrystalline silicon. Accordingly, a capacitance does not decrease, as is described in the semiconductor storage device described in Japanese Patent Laid-Open Publication No. 176148/1986.
In the semiconductor storage device of FIG. 60, polycrystalline silicon is buried in the through-holes 98, 100 to connect the source diffused layers 24 to the capacitor storage electrodes 46, and the drain diffused layers 26 to the bit lines 62, and an extra lithography step of opening the filled through-holes 98, 100 is needed. In comparison with the semiconductor storage device described in Japanese Patent Laid-Open Publication No. 176148/1986, one lithography step is added.
An object of the present invention is to provide a semiconductor storage device and a method for fabricating the same which can decrease a memory cell area by decreasing an alignment allowance in lithography steps, and can decrease a number of the lithography steps.
Another object of the present invention is to provide a semiconductor storage device and a method for fabricating the same which can facilitate etching the contact hole for the capacitor storage electrode, and can decrease a number of fabrication steps.
The above-described objects are achieved by a semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer formed in; a capacitor having a capacitor storage electrode formed on inside walls and a bottom of the first though-hole and connected to the first diffused layer, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a first contact conducting film formed on inside walls and a bottom of the second through-hole and connected to the second diffused layer; a third insulation film formed on the memory cell and having a bit line contact hole formed in; and a bit line formed on the third insulation film and connected to the first contact conducting film of the memory cell through the bit line contact hole. This structure of the semiconductor storage device makes it unnecessary to secure an alignment allowance for alignment of the first through-hole opened on the first diffused layer and the second through-hole opened on the second diffused layer with the gate electrode, which permits the semiconductor storage device to have small memory cell area. It is not necessary to bury the first contact conducting film completely in the second through-hole, which makes it unnecessary to excessively increase the thickness of the capacitor storage electrode, and decrease of the capacitance can be prevented.
The above-described objects are achieved also by a semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer formed in; a first buried conductor buried on a bottom of the first through-hole and connected to the first diffused layer; a second buried conductor buried on a bottom of the second through-hole and connected to the second diffused layer; and a capacitor having a capacitor storage electrode formed on inside walls of the first through-hole and an upper surface of the first buried conductor and connected to the first diffused layer through the first buried conductor, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a first contact conducting film formed on inside walls of the second through-hole and an upper surface of the second buried conductor and connected to the second diffused layer through the second buried conductor; a third insulation film formed on the memory cell and having a bit line contact hole formed in; and a bit line formed on the third insulation film and connected to the first contact conducting film of the memory cell through the bit line contact hole. In this structure of the semiconductor storage device, in forming the through-holes, etc. having high aspect ratios, buried conductors of low resistance are beforehand formed in the region contacting the semiconductor substrate to form an ohmic contact. This ensures contact characteristics at the bottoms of the through-holes even in a case that the through-holes have a higher aspect ratio as the device are higher integrated.
The above-described objects can be achieved also by a semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a second insulation film covering a top of the memory cell transistor, and having a first through-hole opened on the first diffused layer, a second through-hole opened on the second diffused layer and an opening having a larger opening diameter than the first through-hole and formed in a region spaced from the semiconductor substrate, surrounding the first through-hole; a capacitor having a capacitor storage electrode formed on inside walls and a bottom of the opening and on inside walls and a bottom of the first through-hole, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode, covering at least a part of the capacitor dielectric film; and a first contact conducting film formed on inside walls and a bottom of the second through-hole and connected to the second diffused layer; a third insulation film formed on the memory cell and having a bit line contact hole formed in; and a bit line formed on the third insulation film and connected to the first contact conductor film of the memory cell through the bit line contact hole. This structure of the semiconductor storage device makes it possible to make the opening diameter of the through-holes very small without decrease of a capacitance, whereby short-circuit between the bit lines and the word lines due to dust staying in the through-holes can be prevented.
In the above-described semiconductor storage device, it is preferable that the capacitor storage electrode has a first columnar conductor formed in the first though-hole, spaced from the inside walls of the first though-hole; and the first contact conducting film has a second columnar conductor formed in the second through-hole, spaced from the inside walls of the second through-hole. The first columnar conductor also functions as the capacitor storage electrodes, whereby the capacitance can be drastically increased. The wiring between the second diffused layer and the bit line is formed of the first contact conducting film and the second columnar conductor, whereby the wiring resistance of the wiring between the second diffused layer to the bit line can be decreased.
In the above-described semiconductor storage device, it is preferable that the second insulation film in a region contacting the first insulation film is formed of a material having etching characteristics different from those of the first insulation film. In this structure of the semiconductor storage device, the first insulation film can be used as an etching stopper in opening the though-holes, and the openings on the substrate can be formed by self-alignment. Accordingly, it is not necessary to ensure an alignment allowance with the gate electrode in forming the through-holes. The semiconductor storage device can have a small memory cell area.
In the above-described semiconductor storage device, it is preferable that the first insulation film is silicon nitride film; and the material having etching characteristics different from those of the first insulation film is silicon oxide film or impurity-doped silicon oxide film.
In the above-described semiconductor storage device, it is preferable that the capacitor storage electrode further includes a columnar conductor projected in a column-shape in the opening out of the first through-hole, whereby the capacitor storage electrode has an increased area by that of the columnar conductor, and an increased capacitance can be obtained.
In the above-described semiconductor storage device, it is preferable that the device further comprises a sidewall insulation film formed on the inside walls of the bit line contact hole; and the bit line is insulated with respect to the capacitor opposed electrode by the sidewall insulation film. The structure of the semiconductor storage device permits the lithography step of forming the capacitor opposed electrode and the lithography step of forming the bit line contact hole to be concurrently conducted.
In the above-described semiconductor storage device, it is preferable that the device further comprises a peripheral circuit transistor formed on the semiconductor substrate on a periphery of a memory cell region where the memory cell is formed, and a wiring layer formed on the second insulation film and formed of the same conducting layer as the bit line; and the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor. This structure of the semiconductor storage device permits the above-described semiconductor storage device to be fabricated without sacrificing operational speeds of peripheral circuits.
In the above-described semiconductor storage device, it is preferable that the device further comprises a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, a fourth insulation film formed on the bit line, and a wiring layer formed on the fourth insulation film; and in which the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor. This structure of the semiconductor storage device permits the semiconductor storage device to be fabricated without adding to the number of steps of the fabrication and without sacrificing operational speeds of peripheral circuits.
In the above-described semiconductor storage device, it is preferable that the wiring layer is directly connected to the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistor, the capacitor opposed electrode, or the bit line. This structure of the semiconductor storage device permits the semiconductor storage device to be fabricated without adding to the number of steps of the fabrication and without sacrificing operational speeds of peripheral circuits.
In the above-described semiconductor storage device, it is preferable that the device further comprises an etching protection pattern provided directly below the bit line in a region where the bit line and the wiring layer are connected to each other and having the same structure of a laminated film of the capacitor opposed electrode and the third insulation film. This structure of the semiconductor storage device allows the deep through-holes formed in the peripheral circuit region and the shallow through-holes formed on the bit lines or the capacitor opposed electrodes to be concurrently opened without generating short-circuits between the bit line and the semiconductor substrate.
In the above-described semiconductor storage device, it is preferable that the device further comprises a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, and a wiring layer formed on the third insulation film and formed of the same conducting layer as the bit line; and in which the capacitor opposed electrode and the third insulation film are formed extended in a region where the peripheral circuit transistor is formed, and the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor. This structure of the semiconductor storage device makes it possible to form the wiring layers of peripheral circuits without adding to the number of fabrication steps.
In the above-described semiconductor storage device, it is preferable that the device further comprises a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, and a second contact conductor film formed on inside walls and a bottom of a third through-hole formed in the second insulation film on a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor; and in which the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistors are connected, through the second contact conducting film, to a wiring layer formed on the second insulation film. This structure of the semiconductor storage device makes it possible to fabricate the above-described semiconductor storage device without adding to the number of fabrication steps.
In the above-described semiconductor storage device, it is preferable that the device further comprises a third buried conductor formed on a bottom of the third though-hole; and in which the second contact conducting film is connected to the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistor through the third buried conductor. In this structure of the semiconductor storage device, in forming the through-holes, etc. having high aspect ratios, buried conductors of low resistance are beforehand formed in the region contacting the semiconductor substrate to form an ohmic contact. This ensures good contact characteristics at the bottoms of the through-holes even in a case that the through-holes have a higher aspect ratio as the device becomes more higher integrated.
In the above-described semiconductor storage device, it is preferable that the second insulation film is a laminated film of a plurality of insulation materials having different etching characteristics from each other. This structure of the semiconductor storage device makes it easy to open the through-holes even when the through-holes have a high aspect ratio.
In the above-described semiconductor storage device, it is preferable that the laminated film comprises a silicon nitride film, and silicon oxide films sandwiching the silicon nitride film.
In the above-described semiconductor storage device, it is preferable that the laminated film comprises a silicon nitride film laid on a silicon oxide film.
The above-described objects can be achieved also by a semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer; and a capacitor having a capacitor storage electrode having contact formed on inside walls and a bottom of the first through-hole and connected to the first diffused layer and having a projection formed projecting on the second insulation film and connected to the contact, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film. This structure of the semiconductor storage device permits constituting the capacitor with the inside walls and the outside walls of the projection, which can increase the capacitance.
In the above-described semiconductor storage device, it is preferable that the device further comprises a third insulation film formed on the memory cell and having bit line contact hole reaching the second diffused layer through the second insulation film formed in; and a bit line formed on the third insulation film and connected to the second diffused layer of the memory cell through the bit line contact hole.
In the above-described semiconductor storage device, it is preferable that a second through-hole is formed in the second insulation film and is opened on the second diffused layer; and which further comprises a contact conducting film formed on inside walls and a bottom of the second through-hole and connected to the second diffused layer, and a bit line formed on the memory cell through the third insulation film and connected to the contact conducting film.
In the above-described semiconductor storage device, it is preferable that the second insulation film comprises a silicon nitride film and a silicon oxide film; the silicon nitride film is formed on the gate electrode; the silicon oxide film is formed on the silicon nitride film; and the third insulation film comprises a silicon oxide film. This structure of the semiconductor storage device makes it easy to form the projection, and capacitance deviations can be reduced.
In the above-described semiconductor storage device, it is preferable that the first contact conducting film, the second contact conducting film or the capacitor storage electrode are formed of a conducting material which contacts n-silicon and p-silicon. This structure of the semiconductor storage device can improve contact characteristics with the silicon substrate as the semiconductor substrate.
In the above-described semiconductor storage device, it is preferable that the bit line contact hole is elongated in the direction of the bit line. This structure of the semiconductor storage device allows the bit lines and the word lines to be arranged in minimum process dimensions. The semiconductor storage device can have a small memory cell area.
In the above-described semiconductor storage device, it is preferable that the bit line has a film thickness which is below half a gap between the bit lines. This structure of the semiconductor storage device allows capacity coupling between the bit lines to be reduced.
The above-described objects can be achieved also by a semiconductor storage device comprising: a plurality of bit lines arranged parallel with each other; a plurality of word lines arranged parallel with each other and intersecting said plurality of bit lines; sense amplifiers disposed on one end of the respective bit lines; decoders disposed on one end of the respective word lines; and above-described memory cells respectively disposed at intersections of the bit lines and the word lines; said plural sense amplifiers being divided into two groups, the groups of the sense amplifiers being disposed respectively on opposed sides of a memory cell region where the memory cells are formed; said plural decoders being divided into two groups, the groups of the decoders being disposed respectively on opposed sides of the memory cell region where the memory cells are formed. This structure of the semiconductor storage device allows a peripheral circuit to be connected to the bit lines and the word lines to be arranged with minimum processing dimensions.
The above-described objects can be achieved also by a semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer; a buried conductor buried in the first through-hole: and a capacitor having a capacitor storage electrode formed on the second insulation film and connected to the first diffused layer through the buried conductor, a capacitor dielectric film formed covering the capacitor storage electrode and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a bit line formed on the second insulation film and connected to the second diffused layer through the second through-hole; the buried conductor and the bit line being formed of the same conducting layer. This structure of the semiconductor storage device can reduce the etching time for opening the through-holes for contact with the capacitor storage electrode, whereby the exposure of the bit line in the etching can be prevented.
In the above-described semiconductor storage device, it is preferable that the buried conductor is formed on sidewalls and a bottom of the first through-hole.
In the above-described semiconductor storage device, it is preferable that the first through-hole and the second through-hole are formed spaced outward from the gate electrode.
In the above-described semiconductor storage device, is preferable that an upper surface and side surfaces of the bit line are covered with a first insulation film which functions as an etching stopper with respect to a third insulation film formed on the bit line. This structure of the semiconductor storage device can reduce damage to the bit line in opening the through-hole for contact with the capacitor storage electrode.
In the above-described semiconductor storage device, it is preferable that the third insulation film has a third through-hole formed in, the buried conductor being exposed in the third through-hole; and the capacitor dielectric film is formed on sidewalls and a bottom of the third through-hole. This structure of the semiconductor storage device can reduce the height difference between the peripheral circuit region and the memory cell region, which permits the design rule of the wiring layers formed thereabove to be reduced.
The above-described objects can be achieved also by a semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer; a buried conductor buried in the first through-hole: and a capacitor having a capacitor storage electrode formed on the first insulation film and connected to the first diffused layer through the buried conductor, a capacitor dielectric film formed covering the capacitor storage electrode and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a bit line formed on the first insulation film and connected to the second diffused layer through the second through-hole; the buried conductor and the bit line being formed of the same conducting layer. This structure of the semiconductor storage device can reduce the etching time for opening the through-holes for contact with the capacitor storage electrode, whereby the exposure of the bit line in the etching can be prevented.
In the above-described semiconductor storage device, it is preferable that the buried conductor is formed on sidewalls and a bottom of the first through-hole.
In the above-described semiconductor storage device, it is preferable that the first through-hole and the second through-hole are formed spaced outward from the gate electrode.
In the above-described semiconductor storage device, is preferable that an upper surface and side surfaces of the bit line are covered with an insulation film which functions as an etching stopper with respect to a second insulation film formed on the bit line. This structure of the semiconductor storage device can reduce damage to the bit line in opening the through-hole for contact with the capacitor storage electrode.
In the above-described semiconductor storage device, it is preferable that the second insulation film has a third through-hole formed in, the buried conductor being exposed in the third through-hole; and the capacitor dielectric film is formed on sidewalls and a bottom of the third through-hole. This structure of the semiconductor storage device can reduce the height difference between the peripheral circuit region and the memory cell region, which permits the design rule of the wiring layers formed thereabove to be reduced.
The above-described objects can be achieved also by a method for fabricating a semiconductor storage device comprising: a gate electrode forming step of depositing a first conducting film and a first insulation film the latter on the former on a semiconductor substrate and then patterning the first conducting film and the first insulation film to form gate electrodes formed of the first conducting film and having upper surfaces covered with the first insulation film; a diffused layer forming step of doping the semiconductor substrate with an impurity with the gate electrodes as a mask to form first diffused layers and second diffused layers; a first sidewall insulation film forming step of forming first sidewall insulation films on sidewalls of the gate electrodes; a first insulation film forming step of forming a second insulation film having first through-holes and second through-holes formed in, the first through-holes being opened on the first diffused layer, the second through-holes being opened on the second diffused layer; a second conducting film depositing step of depositing a second conducting film on the semiconductor substrate having the second insulation film formed on; a conducting film removing step of removing the second conducting film on the second insulation film, leaving the second conducting film in the first through-holes and the second through-holes to form capacitor storage electrodes of the second conducting film in the first through-holes and first contact conducting films of the second conducting film formed in the second through-holes; and a capacitor opposed electrode forming step of depositing a third insulation film to be capacitor dielectric films and a third conducting film to be capacitor opposed electrodes on the semiconductor substrate with the capacitor storage electrodes and the first contact conducting film and then patterning the third conducting film to form the capacitor opposed electrodes. The method for fabricating a semiconductor storage device enables the semiconductor storage device having a small memory cell area to be fabricated without increasing the electric resistance between the bit lines and the second diffused layers and without decreasing the capacitance.
In the above-described method for fabricating a semiconductor storage device, it is preferable that in the capacitor opposed electrode forming step, a fourth insulation film deposited on the third conducting film and the third conducting film are patterned to form the capacitor opposed electrodes and bit line contact holes opened on the second through-holes; and which further comprises a second sidewall insulation film forming step of depositing a fifth insulation film after the capacitor opposed electrode forming step and anisotropically etching the fifth insulation film for second sidewall insulation films on inside walls of the bit line contact holes while concurrently therewith removing the third insulation films on bottoms of the bit line contact holes; and a bit line forming step of forming bit lines formed on the fourth insulation film and connected to the first contact conducting film exposed in the bit line contact holes. This method permits the lithography step of forming the capacitor opposed electrodes and the lithography step of forming the bit line contact holes to be simultaneously conducted.
The above-described objects can be achieved also by a method for fabricating a semiconductor storage device comprising: a gate electrode forming step of depositing a first conducting film and a first insulation film the latter on the former on a semiconductor substrate and then patterning the first conducting film and the first insulation film to form first gate electrodes of the first conducting film having upper surfaces covered with the first insulation film in a first region for memory cell transistors to be formed in and second gate electrodes of the first conducting film having upper surfaces covered with the first insulation film in a second region for peripheral circuit transistors to be formed in; a diffused layer forming step of doping the semiconductor substrate with an impurity with the gate electrodes as a mask to form in the first region first diffused layers and second diffused layers of the memory cell transistors and in the second region first diffused layers and second diffused layers of the peripheral circuit transistors; a first sidewall insulation film forming step of forming first sidewall insulation films on sidewalls of the gate electrodes; a first insulation film forming step of forming a second insulation film having first through-holes and second through-holes formed in, the first through-holes being opened on the first diffused layer of the memory cell transistors, the second through-holes being opened on the second diffused layers of the memory cell transistors; a second conducting film depositing step of depositing a second conducting film on the semiconductor substrate having the second insulation film formed on; a conducting film removing step of removing the second conducting film on the second insulation film, leaving the second conducting film in the first through-holes and the second through-holes to form capacitor storage electrodes of the second conducting film formed in the first through-holes and the first contact conducting film of the second conducting film formed in the second through-holes; a bit line contact hole forming step of depositing a third insulation film to be capacitor dielectric films, a third conducting film to be capacitor opposed electrodes and a fourth insulation film on the capacitor storage electrodes and the first contact conducting film and then patterning the fourth insulation film and the third conducting film to form the capacitor opposed electrodes and bit line contact holes opened on the second through-holes; a second sidewall insulation film forming step of depositing a fifth insulation film on the fourth insulation film with the bit line contact holes and then anisotropically etching the fifth insulation film to form second sidewall insulation films on inside walls of the bit line contact holes while concurrently therewith removing the third insulation film on bottoms of the bit line contact holes; a second though-hole forming step of forming third through-holes opened on the fourth insulation film on the capacitor opposed electrodes and fourth through-holes formed in the second insulation film opened on the first diffused layers or the second diffused layers of the peripheral circuit transistors, or the second gate electrodes; and a wiring layer forming step of forming bit lines connected to the first contact conducting film exposed in the bit line contact holes, first wiring layers connected to the capacitor opposed electrodes through the third through-hole and second wiring layers connected to the peripheral circuit transistors through the fourth through-holes. This method allows the semiconductor storage device to be fabricated without sacrificing operational speeds of peripheral circuits.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the method further comprises: after the second sidewall insulation film forming step, a bit line forming step of forming bit lines connected to the contact conducting film exposed in the bit line contact holes, a second insulation film forming step of forming a sixth insulation film on the semiconductor substrate with the bit line formed thereon; and in which in the second through-hole forming step, third through-holes reaching the capacitor opposed electrodes are formed in the sixth insulation film and the fourth insulation film, and fourth through-holes reaching the first diffused layers or the second diffused layers of the peripheral circuit transistors, or the second gate electrodes are formed in the sixth insulation film and the second insulation film; and in the wiring layer forming step, first wiring layers connected to the capacitor opposed electrodes through the third through-holes, and second wiring layers connected to the peripheral circuit transistors through the fourth through-holes are formed. This method can fabricate the semiconductor storage device without adding to the number of fabrication steps and sacrificing operational speeds peripheral circuits.
In the above-described method for fabricating a semiconductor storage device, it is preferable that in the second through-hole forming step, when fifth through-holes for connecting the bit lines and the wiring layers are formed, in the bit line contact hole forming step, an etching protection pattern of the laminated film of the third conducting film and the fourth insulation film is formed on the second insulation film in a region where contact holes for connecting the bit lines and the wiring layers are to be formed. This method can prevent etching of the second insulation film directly below the bit lines even in opening the deep through-holes in the peripheral circuit region, whereby short-circuit between the bit lines and the semiconductor substrate can be prevented.
The above-described objects can be achieved also by a method for fabricating a semiconductor storage device comprising: a gate electrode forming step of depositing a first conducting film and a first insulation film the latter on the former on a semiconductor substrate and then patterning the first conducting film and the first insulation film to form first gate electrodes of the first conducting film having upper surfaces covered with the first insulation film in a first region where memory cell transistors are to be formed and second gate electrodes having upper surfaces covered with the first insulation film in a second region where peripheral circuit transistors are to be formed; a diffused layer forming step of doping the semiconductor substrate with an impurity with the gate electrodes as a mask to form first diffused layers and second diffused layers of the memory cell transistors in the first region and first diffused layers and second diffused layers of the peripheral circuit transistors in the second region; a first sidewall insulation film forming step of forming first sidewall insulation films on sidewalls of the gate electrodes; a first insulation film forming step of forming a second insulation film having first through-holes and second through-holes formed in, the first through-holes being opened on the first diffused layers of the memory cell transistors, the second though-holes being opened on the second diffused layers of the memory cell transistors; a second conducting film depositing step of depositing a second conducting film on the semiconductor substrate having the second insulation film formed on; a conducting film removing step of removing the second conducting film on the second insulation film, leaving the second conducting film in the first though-holes and the second through-holes to form capacitor storage electrodes of the second conducting film formed in the first through-holes and first contact conducting film of the second conducting film formed in the second though-holes; a bit line contact hole forming step of depositing a third insulation film to be capacitor dielectric films, a third conducting film to be capacitor opposed electrodes and a fourth insulation film on the capacitor storage electrodes and the first contact conducting film and then patterning the fourth insulation film and the third conducting film to form the capacitor opposed electrodes and bit line contact holes opened on the second though-holes and to open third through-holes onto the third insulation film which are to be opened on the first diffused layers or the second diffused layers of the peripheral circuit transistors or the second gate electrodes; and a second through-hole forming step of selectively forming a photo-resist covering the bit line contact holes and then etching the third insulation film in the third through-holes and the second insulation film to form the third through-holes extending to the first diffused layers or the second diffused layers of the peripheral circuit transistors or the second gate electrodes. This method requires no subtle alignment in opening the through-holes in the peripheral circuit region, which simplifies the lithography steps.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the bit line contact hole forming step, the third insulation film to be capacitor dielectric films, the third conducting film to be capacitor opposed electrodes, the fourth insulation film and a mask film functioning as an etching stopper are successively deposited on the capacitor storage electrodes and the second conducting film, and then the mask film, the fourth insulation film and the third conducting film are patterned, to form the capacitor opposed electrodes and bit line contact holes opened on the second through-holes, and to open onto the third insulation film the third though-holes which are to be opened on the first diffused layers or the second diffused layers of the peripheral circuit transistors or the second gate electrodes; and in the second through-hole forming step, a photo-resist for covering the bit line contact holes is selectively formed, and then with the mask film and the photo-resist as an etching mask, the third insulation film in the third through-holes and the second insulation film are etched to form the third through-holes extending to the first diffused layers or the second diffused layers of the peripheral circuit transistors or the second gate electrodes. This method can simplify the lithography steps.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the mask film is silicon film.
The above-described objects can be achieved also by a method for fabricating a semiconductor storage device comprising: a gate electrode forming step of depositing a first conducting film and a first insulation film the latter on the former on a semiconductor substrate and then patterning the first conducting film and the first insulation film to form first gate electrodes of the first conducting film having upper surfaces covered with the first insulation films in a first region where memory cell transistors are to be formed and to form second gate electrodes of the first conducting film having upper surfaces covered with the first insulation film in a second region where peripheral circuit transistors are to be formed; a diffused layer forming step of doping the semiconductor substrate with an impurity with the gate electrodes as a mask to form first diffused layers and second diffused layers of the memory cell transistors in the first region and to form first diffused layers and second diffused layers of the peripheral circuit transistors in the second region; a first sidewall insulation film forming step of forming first sidewall insulation films on sidewalls of the gate electrodes; a first insulation film forming step of forming a second insulation film having first-through holes, second through-holes, and third through-holes formed in, the first through-holes being opened on the first diffused layers of the memory cell transistors, the second through-holes being opened on the second diffused layers of the memory cell transistors and the third through-holes opened on the first diffused layer or the second diffused layers of the peripheral circuit transistors or the second gate electrodes; a second conducting film depositing step of depositing a second conducting film on the semiconductor substrate having the second insulation film formed on; a conducting film removing step of removing the second conducting film on the second insulation film, leaving the second conducting film in the first through-holes, the second through-holes and the third through-holes to form capacitor storage electrodes of the second conducting film formed in the first through-holes, first contact conducting films of the second conducting film formed in the second through-holes and second contact conducting films of the second conducting film formed in the third through-holes; a bit line contact hole forming step of depositing a third insulation film to be capacitor dielectric films, a third conducting film to be capacitor opposed electrodes and a fourth insulation film on the semiconductor substrate with the capacitor storage electrodes, the first contact conducting films and the second contact conducting films formed on and then patterning the fourth insulation film and the third conducting film to form the capacitor opposed electrodes and bit line contact holes opened on the second through-holes; a second sidewall insulation film forming step of depositing a fifth insulation film on the fourth insulation film with the bit line contact holes formed in and then anisotropically etching the fifth insulation film to form second sidewall insulation films on inside walls of the bit line contact holes while concurrently therewith removing the third insulation film on bottoms of the bit line contact holes; and a wiring layer forming step of forming bit lines connected to the first contact conducting films exposed in the bit line contact holes and wiring layers connected to the second contact conducting films formed in the third through-holes. This method can fabricate the semiconductor storage device without adding to the number of fabrication steps.
In the above-described method for fabricating a semiconductor storage device, it is preferable that in the capacitor opposed electrode forming step, a third conducting film is buried in the first through-holes or the second through-holes to planarize a surface of the third conducting film. This method can simultaneously conduct the lithography step of forming the capacitor opposed electrodes and the lithography step of forming the bit line contact holes.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the method further comprises: after the second conducting film depositing step, a third sidewall insulation film forming step of depositing a seventh insulation film and anisotropically etching the seventh insulation film to form third sidewall insulation films on inside walls of the first through-holes and the second through-holes with the second conducting film formed thereon, and a fourth conducting film depositing step of depositing a fourth conducting film to fill the first through-holes and the second through-holes having the third sidewall insulation films formed on; and further comprising: after the conducting film removing step, a columnar conductor forming step of removing the third sidewall insulation film to form first columnar conductors of the fourth conducting film in the first through-holes and second columnar conductors of the fourth conducting film in the second through-holes, in the conducting film removing step, the fourth conducting film, the second conducting film and the second insulation film are removed until surfaces of the third sidewall insulation films are exposed. This method can fabricate the first columnar conductors so as to function as the capacitor storage electrodes and the second columnar conductors so as to function as the wiring between the second diffused layers and the bit lines, whereby the capacitance can be drastically increased and the wiring resistance of the wiring between the second diffused layers-the bit lines can be decreased. This method can also prevent, in polishing the second conducting film, the polishing agent, etc. from intruding into the though-holes, whereby resultant low yields can be precluded.
In the above-described method for fabricating a semiconductor storage device, it is preferable that in the first insulation film forming step, a second insulation film is deposited and then is polished to planarize a surface of the second insulation film before the though-holes are formed. This method can improve the global planarization on the second insulation film, whereby the depth of focus for opening the through-holes can be small, and micronized patterns can be made.
In the above-described method for fabricating a semiconductor storage device, it is preferable that in the conducting film removing step, a surface of the semiconductor substrate is polished to remove the second conducting film on the second insulation film. This method can easily form the capacitor storage electrodes and the contact conducting films having the through-holes whose configurations are aligned.
In the above-described method for fabricating a semiconductor storage device, it is preferable that in the first insulation film forming step, a second insulation film is formed of a laminated film of a plurality of insulation materials having different etching characteristics from each other, and the insulation materials are etched one by one to open the through-holes. This method can easily open through-holes having high aspect ratios.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the method further comprises: after the second conducting film depositing step, a photo-resist application step of applying a photo-resist to the second conducting film to fill the first through-holes, the second through-holes or the third through-holes; and after the conducting film removing step, a photo-resist releasing step of releasing the photo-resist buried in the through-holes, the second through-holes or the third through-holes,in the conducting film removing step, the second conducting film and the photo-resist on the second insulation film are removed, leaving the second conducting film and the photo-resist in the first through-holes, the second through-holes or the third through-holes. This method can prevent, in polishing the second conducting film, the polishing agent, etc. from intruding into the through-holes, whereby resultant low yields can be precluded.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the method further comprises: after the second conducting film depositing step, an insulation film depositing step of depositing a eighth insulation film having etching characteristics different from those of the second insulation film to fill the first through-holes the second through-holes or the third through-holes; after the conducting film removing step, an insulation film removing step of removing the eighth insulation film buried in the first through-holes, the second through-holes or the third through-holes, in the conducting film removing step, a second conducting film and the eighth insulation film on the second insulation film are removed, leaving the second conducting film and the eighth insulation film in the first through-holes, the second through-holes and third through-holes. This method can prevent, in polishing the second conducting film, the polishing agent, etc. from intruding into the through-holes, whereby resultant low yields can be precluded.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the second insulation film is a laminated film having an insulation film having on a surface thereof etching characteristics different from those of the eighth insulation film. This method makes it possible to selectively remove, after the polishing, only the insulation film buried in the through-holes.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the method further comprises: after the second conducting film depositing step, an insulation film depositing step of depositing a eighth insulation film having etching characteristics substantially the same as those of the second insulation film to fill the first through-holes, the second through-holes or the third through-holes; and after the conducting film removing step, an insulation film removing step of removing the eighth insulation film buried in first through-holes, the second through-holes or the third through-holes, leaving the second conducting film and the eighth insulation film in the first through-holes, the second through-hole or the third through-holes. This method can prevent, in polishing the second conducting film, the polishing agent, etc. from intruding into the through-holes, whereby resultant low yields can be precluded.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the second insulation film is a laminated film of an insulation film having substantially the same etching characteristics as those of the eighth insulation film deposited on an insulation film having etching characteristics different from those of the eighth insulation film,in the insulation film removing step a eighth insulation film and the insulation film having substantially the same etching characteristics are removed. This method makes it possible to selectively remove, in the insulation film removing step, the eighth insulation film and the insulation film having substantially the same etching characteristics as the eighth insulation film.
The above-described objects can be achieved also by a method for fabricating a semiconductor storage device comprising: a gate electrode forming step of depositing a first conducting film and a first insulation film the latter on the former on a semiconductor substrate and then patterning the first conducting film and the first insulation film to form first gate electrodes of the first conducting film having upper surfaces covered with the first insulation film in a first region where memory cell transistors are to be formed, and second gate electrodes of the first conducting film having upper surfaces covered with the first insulation film in a second region where peripheral circuit transistors are to be formed; a diffused layer forming step of doping the semiconductor substrate with an impurity with the gate electrodes as a mask to form first diffused layers and second diffused layers of the memory cell transistors in the first region, and first diffused layers and second diffused layers of the peripheral circuit transistors in the second region; a first sidewall insulation film forming step of forming first sidewall insulation films on sidewalls of the gate electrodes; a first insulation film forming step of depositing a second insulation film on the semiconductor substrate with the first sidewall insulation films and then planarizing a surface of the second insulation film;e a third insulation film forming step of forming a third insulation film having etching characteristics different from those of the second insulation film on the planarized second insulation film; a through-hole forming step of patterning the second insulation film and the third insulation film to open first through-holes to be opened on the first diffused layers, second through-holes to be opened on the second diffused layers, and third though-holes to be opened on the first diffused layers or the second diffused layers of the peripheral circuit transistors, or the second gate electrodes; a second conducting film depositing step of depositing a second conducting film having the through-holes formed in on the semiconductor substrate; a buried conductor forming step of polishing a surface of the second conducting film until the third insulation film is exposed on a surface to form first buried conductors buried in the first through-holes, second buried conductors buried in the second through-holes and third buried conductors buried in the third through-holes; a third insulation film forming step of forming a fourth insulation film with fourth through-holes opened on the first buried conductors, fifth through-holes opened on the second buried conductors and sixth holes opened on the third buried conductors; a third conducting film depositing step of depositing a third conducting film on the semiconductor substrate with the fourth insulation film formed; and a conducting film removing step of removing the third conducting film on the fourth insulation film, leaving the second conducting film in the fourth though-holes, the fifth through-holes and the sixth through-holes to form capacitor storage electrodes of the third conducting film in the fourth through-holes, first contact conducting film of the third conducting film formed in the fifth through-holes and second contact conducting film of the third conducting film formed in the sixth contact holes. This method can secure good contact characteristics at the bottoms of the through-holes even in the case that the through-holes have higher aspect ratios with higher device integration.
In the above-described method for fabricating a semiconductor storage device, it is preferable that in the conducting film removing step, a surface of the semiconductor substrate is polished to remove the third conducting film on a surface of the fourth insulation film. This method can form the buried conductors simultaneously with planarization of the insulation film.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the first sidewall insulation films and the first insulation film function as an etching stopper for forming the through-holes; and the through-holes are formed by self-alignment with the first insulation film and the first sidewall insulation films. This method can easily expose the first diffused layers and the second diffused layers on the bottoms of the through-holes.
The above-described objects can be achieved also by a method for fabricating a semiconductor storage device comprising: a gate electrode forming step of depositing and patterning a first conducting film on a semiconductor substrate to form gate electrodes of the first conducting film; a diffused layer forming step of doping the semiconductor substrate with an impurity with the gate electrodes as a mask to form first diffused layers and second diffused layers; a first insulation film forming step of forming a first insulation film having first through-holes and second through-holes formed in, the first through-holes opened on the first diffused layers and the second through-holes opened on the second diffused layers; an opening forming step of forming openings in the first insulation film, surrounding the first through-holes, the opening having a larger diameter than the first though-holes and not reaching the semiconductor substrate; a second conducting film depositing step of depositing a second conducting film on the semiconductor substrate having the first insulation film formed on; a conducting film removing step of removing the second conducting film on the first insulation film, leaving the second conducting film in the second through-holes-and the openings to form capacitor storage electrodes of the second conducting film formed in the openings and first contact conducting film of the second conducting film formed in the second though-holes; and a capacitor opposed electrodes forming step of depositing a second insulation film to be capacitor dielectric films and a third conducting film to be capacitor opposed electrodes on the semiconductor substrate with the capacitor storage electrodes and the first contact conducting film formed on and then patterning the third conducting film to form the capacitor opposed electrodes. This method can space the gate electrodes and the though-holes from each other, whereby short-circuit between the bit lines and the word lines due to dust, etc. generated in the fabrication steps can be precluded. The openings for forming the capacitor are provided in addition to the small-diameter through-holes, which prevent capacitance decrease.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the method further comprises: after the first insulation film forming step, a fourth conducting film depositing step of depositing a fourth conducting film to fill the first through-holes and the second through-holes, in the openings forming step the openings being formed leaving columnar conductors of the fourth conducting film buried in the first through-holes in the openings in a projecting state. This method can prevent the semiconductor substrate exposed in the first through-holes in forming the openings from being damaged. The capacitor dielectric films are formed surrounding the columnar conductors, which increases capacitances.
In the above-described method for fabricating a semiconductor storage device, it is preferable that in the first insulation film forming step the first through-holes and the second through-holes are simultaneously formed.
In the above-described method for fabricating a semiconductor storage device, it is preferable that in the first insulation film forming step, the first insulation film is formed of a laminated film of two or more than two layers having etching characteristics different from each other; in the opening forming step, the openings are opened to an interface between the laminated film having different etching characteristics from each other. This method can control a depth of the openings with good reproducibility, which decreases deviations of the capacitance.
The above-described objects can be achieved also by a method for fabricating a semiconductor storage device comprising: a gate electrode forming step of depositing and patterning a first conducting film on a semiconductor substrate to form gate electrodes of the first conducting film; a diffused layer forming step of doping the semiconductor substrate with an impurity with the gate electrodes as a mask to form first diffused layers and second diffused layers; a first insulation film forming step of forming a first insulation film with first though-holes and second through-holes formed in, the first through-holes being opened on the first diffused layers and the second through-holes being opened on the second diffused layers; a second conducting film depositing step of depositing a second conducting film on the semiconductor substrate having the first insulation film formed on; a second conducting film patterning step of patterning the second conducting film to form bit lines connected to the second diffused layers through the first through-holes and buried conductors buried in the second-through-holes; and a capacitor forming step of forming capacitors including capacitor storage electrodes connected to the first diffused layers through the buried conductors, capacitor dielectric films covering the capacitor storage electrodes and capacitor opposed electrodes covering at least a part of the capacitor dielectric films. This method can connect the capacitor storage electrodes with the first diffused layers through the buried conductors buried at the same time that the bit lines have been formed, in the second through-holes formed concurrently with formation of the first through-holes for contact with the bit lines. Accordingly, the etching time for forming the through-holes for contact with the capacitor storage electrodes can be decreased without addition of a new step, whereby the insulation film on the bit lines is kept, in the etching, from being etched and exposed.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the method further comprises: after the second conducting film depositing step, a second insulation film depositing step of depositing a second insulation film on the second conducting film; after the second conducting film patterning step, a sidewall insulation film forming step of forming sidewall insulation films on sidewalls of the bit lines,in the second conducting film patterning step, the second insulation film and the second conducting film are processed in the same pattern. In this method, simultaneously therewith the buried conductors are exposed on the surface. Accordingly, it is unnecessary to form the through-holes for contact with the capacitor storage electrodes, using a masking step. That is, one masking step can be omitted.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the method further comprises: after the second conducting film patterning step, a second insulation film forming step of forming a second insulation film with openings formed on the buried conductors, wherein in the capacitor forming step, the capacitor storage electrodes are selectively formed in sidewalls and bottoms of the openings. The design rule of the wiring layers formed above can be designed with precision.
In the above-described method for fabricating a semiconductor storage device, it is preferable that the first insulation film forming step is characterized by including: a first insulation film depositing step of depositing a first insulation film on the semiconductor substrate; an etching stopper film forming step of forming an etching stopper film with openings in a region for the first through-holes to be formed in and a region for the second through-holes to be formed in and having etching characteristics different from those of the first insulation film; a sidewall forming step of forming sidewalls having etching characteristics different from those of the first insulation film on sidewalls of the etching stopper film; and a through-hole opening step of etching the first insulation film with the etching stopper film and the sidewalls as a mask etching the first insulation film to form the first insulation film with the first through-holes and the second through-holes formed in. This method permits the through-holes to have an opening diameter below a resolution limit of an exposing device.
In the above-described method for fabricating a semiconductor storage device, it is preferable that in the first insulation film forming step, the first insulation film is deposited on the semiconductor film and then etching the first insulation film by electron beam lithography with a patterned photo-resist as a mask to open the first through-holes and the second through-holes. This method permits the first through-holes and the second through holes to have an opening diameter of below a resolution limit of the usual exposing device.